The present invention relates to integrated circuit memory devices and, more particularly, to content addressable memory (CAM) devices and methods of operating same.
In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the device and then performing a search operation to identify one or more entries within the CAM device that contain data equivalent to the applied data and thereby represent a xe2x80x9cmatchxe2x80x9d condition. In this manner, data is accessed according to its content rather than its address. A global search operation is frequently referred to as a xe2x80x9clook-upxe2x80x9d operation and a local search operation is frequently referred to as a cell-based xe2x80x9ccomparexe2x80x9d operation.
Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., CAM array block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM device to identify a highest priority matching entry. An exemplary CAM device that utilizes a priority encoder to identify a highest priority matching entry is disclosed in commonly assigned U.S. Pat. No. 6,370,613 to Diede et al., entitled xe2x80x9cContent Addressable Memory with Longest Match Detect,xe2x80x9d the disclosure of which is hereby incorporated herein by reference. The ""613 patent also discloses the use of CAM sub-arrays to facilitate pipelined search operations. Additional CAM devices are described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and in U.S. Pat. Nos. 6,101,116, 6,256,216, 6,128,207, 6,266,263 and 6,262,907 to Lien et al., the disclosures of which are hereby incorporated herein by reference.
CAM cells are frequently configured as binary CAM cells that store only data bits (as xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d logic values) or as ternary CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an xe2x80x9cunmaskedxe2x80x9d data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a xe2x80x9cdon""t carexe2x80x9d (X) value, which means that a compare operation performed on the actively masked ternary CAM cell during a global search operation will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array block having a plurality of entries therein of logical width N, then a search operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array block are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}.
Operations to perform a conventional compare operation will now be described more fully with respect to FIG. 1A. In particular, FIG. 1A illustrates a conventional ten transistor (10T) CAM cell 10. The CAM cell 10 includes an SRAM data cell and a compare circuit. The SRAM data cell includes first and second access transistors N1 and N2 and first and second inverters that are electrically coupled in antiparallel. The true and complementary inputs of the SRAM data cell are electrically coupled to a true bit line BIT and a complementary bit line BITB, respectively. The true and complementary outputs of the SRAM data cell are illustrated as nodes Q and QB, respectively. The compare circuit includes transistors N3-N6, with the gate of transistor N6 operating as a true data input of the compare circuit and the gate of transistor N4 operating as a complementary data input of the compare circuit. As illustrated, the true data input of the compare circuit is electrically connected to the true data line DATA and the complementary data input of the compare circuit is electrically connected to the complementary data line DATAB. As illustrated by the dotted lines, the true bit line BIT and the complementary data line DATAB may be electrically connected together as a first bit line and the complementary bit line BITB and the true data line DATA may be electrically connected together as a second bit line. The first and second bit lines may be treated as a pair of differential bit/data lines that support rail-to-rail (e.g., Vdd-to-Vss) signals.
The compare circuit is also electrically connected to a pair of signal lines. This pair of signal lines includes a match line (ML) and a pseudo-ground line (PGND) (or ground line (Vss)). The pseudo-ground line PGND may be referred to as a xe2x80x9clowxe2x80x9d match line (LM). The operation of a CAM cell that is responsive to a match line (ML) and low match line (LM) is more fully described in U.S. Pat. No. 6,262,907 to Lien et al., entitled xe2x80x9cTernary CAM Cell,xe2x80x9d assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference.
The match line ML and pseudo-ground line PGND are precharged high prior to a compare operation and then the pseudoground line PGND is pulled low at a commencement of the search operation. During the search operation, the potential of the match line can be monitored to determine whether or not the CAM cell 10 is associated with a matching entry within a CAM array. For example, if the SRAM data cell within the CAM cell 10 is storing a logic 1 value (Q=1 and QB=0) and the illustrated pair of data lines is driven with a matching logic 1 value (i.e., DATA=1 and DATAB=0), then transistors N3 and N6 within the compare circuit will be turned on and transistors N4 and N5 within the compare circuit will remain off. Under these conditions, the series electrical connection provided by transistors N3 and N4 and the series electrical connection provided by transistors N5 and N6 will both remain nonconductive. Accordingly, the CAM cell 10 will not operate to electrically connect (i.e., xe2x80x9cshortxe2x80x9d) the match line and pseudo-ground line PGND together and, therefore, will not operate to pull-down the match line from its precharged high level. In contrast, if the SRAM cell within the CAM cell 10 is storing a logic 0 value (Q=1 and QB=0) and the illustrated pair of data lines is driven with an logic 1 value (i.e., DATA=1 and DATAB=0), then transistors N5 and N6 within the compare circuit will be turned on and transistors N3 and N4 within the compare circuit will remain off. Under these conditions, the series electrical connection provided by transistors N5 and N6 will become conductive and the match line will be pulled-down from its precharged high level.
Referring now to FIG. 2, a conventional nine transistor (9T) CAM cell 12 is illustrated. This CAM cell 12 includes an SRAM data cell and a compare circuit. The compare circuit includes three transistors N7-N9. When the SRAM data cell is storing a logic 1 value (i.e., Q=1 and QB=0), and the pair of differential data lines are driven with a logic 1 value (i.e., DATA=1 and DATAB=0), transistors N7 and N8 will remain off and node N will remain low at its precharged low level. Under these conditions, transistor N9 will remain nonconductive and the CAM cell 12 will not operate to pull the match line low from its precharged high level. In contrast, if the SRAM data cell is storing a logic 0 value (i.e., Q=0 and QB=1), and the pair of differential data lines are driven with a logic 1 value (i.e., DATA=1 and DATAB=0), transistor N7 will remain off, but transistor N8 will turn on and drive node N high from its precharged low level. Under these conditions, transistor N9 will turn on and the CAM cell 12 will pull the match line low from its precharged high level, thereby indicating a xe2x80x9cmissxe2x80x9d condition (i.e., a mismatch between the data stored in the SRAM data cell and the data bit applied to the pair of data lines).
The vertical CAM cell 14 of FIG. 3 includes an SRAM data cell, which is identical to the SRAM data cell of FIG. 1, and a SRAM mask cell. The SRAM mask cell includes access transistors N11 and N12 and a pair of inverters that are electrically connected in antiparallel. The differential outputs of the SRAM mask cell are illustrated as nodes M and MB. The gates of access transistors N11 and N12 are electrically connected to a respective mask line, which operates as a xe2x80x9cwordxe2x80x9d line during operations to write data to and read data from the SRAM mask cell. By convention, the CAM cell 14 of FIG. 3 has three states: 1, 0 and X (don""t care). The X state is achieved by setting the true output node M of the SRAM mask cell to a logic 0 value. When the true output node M of the SRAM mask cell is set to a logic 0 value, transistor N10 within the compare circuit will remain off and preclude the match line and pseudo-ground line PGND from being connected together during a search operation. Accordingly, setting the true output node M of the SRAM mask cell to a logic 0 value operates to actively mask the CAM cell 14 during a search operation and thereby prevents the CAM cell 14 from indicating a cell miss condition by pulling down the match line from its precharged high level. However, when the true output node M of the SRAM mask cell is set to a logic 1 value, the CAM cell 14 is not actively masked and the compare circuit operates in a similar manner to the compare circuit illustrated by FIG. 1.
The vertical CAM cell 16 illustrated by FIG. 4 is similar to the CAM cell 12 of FIG. 2, however, an additional SRAM mask cell is provided and the compare circuit is modified to include an additional transistor N13. The SRAM mask cell of FIG. 4 is identical to the SRAM mask cell of FIG. 3. As will be understood by those skilled in the art, setting the true output M of the SRAM mask cell to a logic 1 value will cause the transistor N13 within the compare circuit to become conductive. When the transistor N13 becomes conductive, the mask associated with the CAM cell 16 is inactive and the compare circuit of FIG. 4 operates identically to the compare circuit of FIG. 2.
Referring now to FIG. 1B. a block diagram of a partially full CAM array 18 undergoing a search operation is provided. Using conventional techniques, the match lines associated with invalid entries in the CAM array 18 may be disabled. The CAM array 18 of FIG. 1B may utilize one or more of the CAM cells described above with respect to FIGS. 1A and 2-4. The CAM array 18 is illustrated as having a maximum depth of 14 rows, with each row supporting an entry having a width of 14 bits. To improve manufacturing yield, the CAM array 18 is also illustrated as including an active redundant column of CAM cells, shown as column R, which replaces a defective normal column, shown as column 7.
Conventional circuitry to enable replacement of a defective column with a redundant column is illustrated by FIGS. 1C-1E. In particular, FIG. 1C illustrates a data line control circuit 40a and a fuse-programmable circuit 50 that enables the data line control circuit 40a when the illustrated fuse is not blown (FB=0) and disables the data line control circuit 40a when the fuse is blown or cut (FB=1) in response to yield testing. The elements of FIG. 1C are typically used to drive a main column of a CAM array. As illustrated by the global mask pass-through circuit 54a, an active low global mask signal (/GM) is provided to the data line control circuit 40a when FB=0. However, once the fuse is blown (and a reset pulse RESET is received), the pass-through circuit 54a operates to clamp the global mask input of the data line control circuit 40a at a logic 0 level, thereby masking the outputs DATA and DATAB in accordance with the illustrated truth table. FIG. 1D illustrates a data line control circuit 40b and a fuse-programmable circuit 50 that disables the data line control circuit 40b when the illustrated fuse is not blown (FB=0), which is the default condition upon manufacture, and enables the data line control circuit 40b when the fuse is blown or cut (FB=1). The elements of FIG. 1D are typically used to drive a redundant column of a CAM array. As illustrated by the global mask pass-through circuit 54b, an active low global mask signal (/GM) is provided to the data line control circuit 40b when FB=1. However, if the fuse is not blown, the pass-through circuit 54b operates to clamp the global mask input of the data line control circuit 40b at a logic 0 level, thereby masking the outputs DATA and DATAB in accordance with the illustrated truth table. Referring now to FIG. 1E, a conventional bit line control circuit 42 is illustrated. The conventional bit line control circuit 42 typically drives respective pairs of differential bit lines BIT and BITB at levels consistent with a conventional read operation (i.e., BIT=BITB=1) by clamping a write control input of the bit line control circuit 42 at a logic 0 level, in response to a blown fuse (i.e., FB=1).
During the performance of a search operation on the CAM array 18 of FIG. 1B, an applied search word having a width of 14 bits is driven onto 14 pairs of complementary comparand data lines (e.g., DATA/DATAB) that span respective active columns of the CAM array 18. In particular, the search word is applied to columns 1-6, 8-14 and R of the CAM array 18, while the defective column 7, which has been disabled by a bit line control circuit (not shown), receives a mask value (i.e., DATA7=DATAB7=0). Based on the illustrated masking of column 7, only row 7 of the CAM array 18 will generate a match condition in response to the search operation.
As will be understood by those skilled in the art, a defective column of a CAM array can be masked during a search operation by pulling and holding both data lines low (i.e., DATA=0 and DATAB=0). Pulling and holding both data lines low operates to disable the compare circuit associated with each CAM cell within the defective column. Thus, in the illustrated example, defective column 7 of the CAM array 18 is masked during each search operation. Because column 7 is masked during each search operation, it has not been necessary for control circuitry associated with the CAM array 18 to intentionally write the data values of the CAM cells in the defective column, because none of the data values within a defective column will be compared with any valid bit of an applied search word. Typically, the data values of the CAM cells in a defective column achieve random or arbitrary states (shown as ?) when the CAM array 18 is powered-up for a first time and one or more of these states may switch every time the CAM array 18 undergoes a power reset event.
A CAM array may also be provided with CAM cells having multiple compare ports that facilitate increased search rates. For example, FIGS. 4-6 of U.S. Pat. No. 6,137,707 illustrates a CAM cell having multiple compare circuits therein that receive distinct comparands during overlapping search cycles. As illustrated by FIG. 4 of the ""707 patent, these comparands (DATA1-DATAn) are used as search words during overlapping search cycles that are synchronized to a single clock signal (CLK).
Notwithstanding the use of redundant columns to improve yield in manufactured CAM devices or the use of CAM cells that perform overlapping search operations, there continues to be a need for CAM devices having higher yield, increased reliability and higher search flexibility when used in an intended application.
Integrated circuit memory devices according to embodiments of the present invention include a content addressable memory (CAM) device having an array of multi-compare port CAM cells therein. These CAM cells are configured to support concurrent search operations between multiple distinct search words and entries within the rows of the CAM array. These concurrent search operations may be performed in-sync with respective clock signals that are asynchronous relative to each other. In particular, the CAM device may include a CAM array that is arranged as a plurality of rows and a plurality of columns of multi-compare port CAM cells. The CAM array is configured to enable comparison between at least first and second search words (or segments thereof) that are applied concurrently to the same multi-compare port CAM cells and data entries stored in the plurality of rows. A control circuit is also provided. This control circuit is configured to provide the CAM array with search control signals that enable the plurality of rows to be searched with the first and second search words during overlapping search cycles. These search cycles are synchronized to separate clock signals, which are asynchronous relative to each other. These clock signals may be derived from clock signals generated external to the CAM device. Each search cycle may also span a plurality of periods of a respective clock signal.
According to preferred aspects of these embodiments, the plurality of rows of multi-compare port CAM cells include first and second rows of CAM cells that share at least first and second independently controllable pseudo-ground lines. The overlapping search cycles may also include a first search cycle that is commenced in-sync with a high-to-low transition of the first pseudo-ground line and a second search cycle that is commenced in-sync with a high-to-low transition of the second pseudo-ground line.
CAM devices according to additional embodiments of the present invention include a CAM array having at least first and second rows of multi-compare port CAM cells therein that share at least first and second independently controllable pseudo-ground lines. A control circuit is also provided. This control circuit is configured to provide the CAM array with search control signals that enable the multi-compare port CAM cells in the first and second rows to be concurrently searched with different search words during first and second overlapping search cycles that are in-sync with first and second clock signals, which are asynchronous relative to each other.
The CAM device also includes a first PMOS pull-up transistor having a first current carrying terminal that is electrically coupled to a first match line associated with the first row of multi-compare port CAM cells. This first PMOS pull-up transistor has a gate terminal that is responsive to a first evaluation signal. A first NMOS pull-up transistor is also provided. The first NMOS pull-up transistor has a first current carrying terminal that is electrically coupled to the first pseudo-ground line. The first NMOS pull-up transistor has a gate terminal that is responsive to a complementary version of the first evaluation signal. A second PMOS pull-up transistor is also provided. The second PMOS pull-up transistor has a first current carrying terminal that is electrically coupled to a first match line associated with the second row of multi-compare port CAM cells and a gate terminal that is responsive to the first evaluation signal.
A CAM array according to a further embodiment of the present invention includes a first lateral multi-compare port CAM cell therein. This lateral CAM cell includes first and second RAM cells and a first compare circuit that is disposed between the first and second RAM cells. The first compare circuit is electrically coupled to: a first pair of differential data lines, first and second outputs of the first and second RAM cells, a first match line and a first pseudo-ground line. The first lateral CAM cell also includes a second compare circuit that disposed between the first and second RAM cells. The second compare circuit is electrically coupled to: a second pair of differential data lines, the first and second outputs of the first and second RAM cells, a second match line and a second pseudo-round line.
An integrated circuit system according to another embodiment of the present invention includes at least a first data processing unit that generates a first clock signal and a second data processing unit that generates a second clock signal, which is asynchronous relative to the first clock signal. A multi-port CAM chip is also provided. The CAM chip includes a first data port that is configured to receive first search words from the first data processing unit, in-sync with the first clock signal. The CAM chip also includes a second data port that is configured to receive second search words from the second data processing unit, in-sync with the second clock signal. The CAM chip also includes a multi-compare port CAM array that is configured to support overlapping first and second search cycles that are synchronized with the first and second clock signals, respectively. According to a preferred aspect of this embodiment, the CAM chip further includes at least one address queue that is configured to retain read addresses, write addresses and write data received from the first and second data processing units. The at least one address queue may have flexible priority support that enables entries therein to be processed out-of-turn during write and/or read operations.
Content addressable memory (CAM) devices according to further embodiments of the present invention provide improved reliability by inhibiting disabled CAM cells within defective columns from contributing to either sustained or intermittent look-up errors when the CAM device is operated in an intended application. The improved reliability is preferably achieved in volatile CAM devices by configuring (e.g., programming) each column driver that is associated with a CAM array having a defective column therein to preserve intentionally written data and/or mask values of the disabled CAM cells across repeated power reset events that may occur at the chip or system level. Still further improvements in reliability can be achieved by configuring each column driver that is associated with a CAM array having an unused redundant column of CAM cells therein to preserve intentionally written data and/or mask values of the CAM cells in the unused redundant column across the power reset events. Preserving these intentionally written data and/or mask values in defective column CAM cells (and/or inactive redundant column CAM cells) operates to reduce the number of CAM cells that are likely to contribute to sustained or intermittent look-up (or other) errors that may occur after a CAM device is tested and shipped to a user.
In particular, CAM devices according to embodiments of the present invention comprise at least one CAM array and a column driver circuit that is electrically coupled to the CAM array by bit lines and/or data lines. The CAM array has a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein. During initial testing, a first one of the main columns of CAM cells may be identified as a defective column and replaced by another column in the CAM array. In response to detecting the defective column during testing, the redundant column of CAM cells may be enabled and used as a replacement for one of the main columns. The column driver circuit, also referred to herein as a bit line driver circuit (or bit/data line driver circuit), is preferably programmed to enable the redundant column and disable the defective column. Once programmed, the column driver circuit may drive at least one disabled CAM cell in the defective column with a respective fixed data value. This operation is preferably performed whenever the at least one disabled CAM cell undergoes a write operation. After being programmed, the CAM device may again be tested to assess yield prior to shipping to the user.
The disabled CAM cell may be a CAM cell having a data RAM cell and a mask RAM cell therein. In this case, the column driver circuit is also preferably programmed to drive the mask RAM cell with a respective fixed mask value whenever the mask RAM cell undergoes a write operation. The data RAM cell and the mask RAM cell may be selected from a group consisting of SRAM cells, DRAM cells and nonvolatile RAM cells (e.g., EEPROM). According to a preferred aspect of this embodiment, the column driver circuit is programmed (e.g. fuse-programmed) to drive the bit lines associated with a defective column with the same fixed data value whenever any one of the disabled CAM cells in the defective column undergoes a write operation.
CAM devices according to further embodiments of the present invention preferably include a CAM array having. a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein. The main and redundant columns of CAM cells are preferably coupled to a bit line driver circuit. In response to yield testing, the bit line driver circuit is programmed to preserve previously written data values of column disabled CAM cells across a power reset event so that each column disabled CAM cell associated with a row containing a valid entry prior to a power reset event is rewritten again with a same data value it had prior to the power reset event. These rewriting operations are performed in sequence as rows within the CAM array are updated with new entries after the power reset event. The column disabled CAM cells include CAM cells located in inactive defective columns and/or unused redundant columns. The column disabled CAM cells are preferably volatile CAM cells that retain one of three states (1, 0, X) that can be evaluated during search operations. Such CAM cells may include a data RAM cell and a mask RAM cell. The CAM cell may be configured so that the mask RAM cell can be read along with the data RAM cell during a reading operation. The bit line driver circuit is also preferably programmed to preserve the mask values of the column disabled CAM cells across a power reset event.
Still further embodiments of the present invention include methods of operating content addressable memory (CAM) devices by writing a first data value and second data/mask value into a CAM cell comprising first and second RAM cells that share a respective word line and are separated by compare logic having true and complementary data inputs that are electrically coupled to a true data line D and a complementary data line DB, respectively. In preparation of a search operation, a match line and a pseudo-ground line associated with a row of CAM cells are precharged high. A potential of the true data line is then at least partially equilibrated with a potential of the complementary data line by transferring charge between the true and complementary data lines. The data lines are then driven rail-to-rail to represent a logic 1 or logic 0 value thereon as a bit of a comparand. An operation to compare a state of the CAM cell with the bit of the comparand is then performed, in response to pulling the precharged pseudo-ground line low. The step to equilibrate data line potentials preferably includes transferring charge from a more positively biased one of the true and complementary data lines to a less positively biased one of the true and complementary data lines for a duration sufficient to achieve a potential difference between the true and complementary data lines that is less than about 30% of a rail-to-rail voltage (i.e., less than about 0.3(Vddxe2x88x92|Vss|)).
A content addressable memory (CAM) device according to another embodiment of the present invention includes a CAM array having a disabled CAM cell therein. The disabled CAM cell includes a first RAM cell and a second RAM cell that share a respective word line. First and second pairs of differential bit lines are also provided. The first pair of differential bit lines (e.g., B1, B1B) are electrically connected to the first RAM cell and the second pair of differential bit lines (e.g., B2, B2B) are electrically connected to the second RAM cell. A bit/data line control circuit is also provided. The bit/data line control circuit is fuse-programmed to clamp and hold a first one of the first pair of differential bit lines (e.g., B1/DB) and a first one of the second pair of differential bit lines (e.g., B2/D) at a first voltage level (e.g., Vss) when the CAM array undergoes reading, writing and search operations.